1. Field of the Invention
The invention relates to an externally controlled power on reset device for a non-volatile memory in integrated circuit form.
2. Discussion of the Related Art
Memory circuits usually have reset circuitry that acts upon the detection of a decrease or a rise in the logic supply voltage Vcc of the integrated circuit.
This is the so-called POR or power-on-reset circuit whose mechanism is used to prevent any memory operation once the supply voltage decreases below a defined lower limit threshold or goes above a defined upper limit threshold. However, a decrease in supply voltage needs to be sufficiently lengthy (in the range of some microseconds) in order to be detected by the POR circuitry.
In an application system, the memory circuit is one of several that are managed by at least one microprocessor circuit or microcontroller circuit to implement an application program.
In this context, it may be useful for the microprocessor to enforce the resetting of the memory circuit. This may be the case when the microprocessor has detected an error in the instructions sent to the memory, this error being due to noise that prompts parasitic pulses on a control signal. This may be the case if the microprocessor has sent certain instructions to the memory circuit and then detected a fall in the supply voltage. It is then desirable that a microprocessor should be capable of stopping the performance of the instructions in the memory circuit. Indeed, the POR circuitry is slow to detect a variation and does not detect excessively rapid voltage decreases.
Furthermore, the POR circuitry is not very precise as regards detection thresholds. For example, for a lower limit threshold set at 3.7 volts, the circuitry will in practice be activated within an interval [3.5-3.9] volts as a function of the ambient temperature, variations in manufacturing method, etc.
The microprocessor for its part comprises very precise and fast detection means. It is therefore appropriate that the microprocessor which detects these variations while it sends instructions to be performed in the memory circuit should be capable of stopping the circuit so as to prevent any error of execution (in memory writing operations).
In particular, in GSM applications, it is very important to have a very precise detection threshold. This is offered by the microprocessor in an application of this kind but not by the POR circuitry of the memory circuit.
In all these cases, which are not exhaustive, there is a definite value in allowing the microprocessor to enforce the resetting of the memory circuit in order to protect it or release it. Furthermore, it may be necessary to enforce the resetting of the memory circuit during industrial testing.
In the prior art, to enforce the resetting of the memory circuit, it is necessary to activate the POR mechanism, namely to enforce a decrease that is sufficiently lengthy (some microseconds) in the logic supply voltage of the memory circuit. It is then necessary to separate the logic supply of the memory circuit from the logic supply of the other circuits of the application system so as not to affect these other circuits in the event of enforced resetting.
Furthermore, it has been seen that the POR circuitry requires a lengthy decrease in voltage which will substantially slow down the application program. In a GSM application in particular, the excessively slow response of the POR circuitry means that the advantages of precise detection by the microprocessor are lost. This problem is found also in the industrial testing of the memory circuit. Indeed the full importance of the testing duration, which has a direct effect on costs and delivery times, is known.